1. Field of the Invention
The present invention relates to a test circuit in which a wafer test is performed for a semiconductor memory by using an external clock signal having a pulse repetition period longer than that of a clock signal actually used in a normal operation of the semiconductor memory.
2. Description of Related Art
A test circuit is generally used for a wafer test of a semiconductor integrated circuit such as a semiconductor memory or the like. In the test circuit, a low frequency clock signal having a pulse repetition period longer than that of a clock signal, which is actually used to perform a normal operation of the semiconductor integrated circuit, is used. Therefore, an operational performance of the semiconductor integrated circuit is tested by using the external clock signal having a pulse repetition period longer than that of a clock signal actually used in a normal operation of the semiconductor integrated circuit. A conventional test circuit of a synchronous dynamic random access memory (SDRAM) representing a semiconductor memory is described with reference to FIG. 8 and FIG. 9.
FIG. 8 is a block diagram of an SDRAM having a conventional test circuit. In FIG. 8, 80 indicates an SDRAM. 81 indicates a conventional test circuit of the SDRAM 80. 82 indicates a flip-flop of the conventional test circuit 81. In the flip-flop 82, an internal write command signal is produced from an external write command signal and an external clock signal. 83 indicates a flip-flop of the conventional test circuit 81. In the flip-flop 83, an internal pre-charge command signal is produced from an external pre-charge command signal and the external clock signal. 84 indicates a memory cell array of the SDRAM 80. In the memory cell array 84, an operation test is performed in a write recovery time-period determined by both the internal write command signal produced in the flip-flop 82 and the internal pre-charge command signal produced in the flip-flop 83.
A wafer test operation of the SDRAM 80 performed by the conventional test circuit 81 is described.
FIG. 9 is a timing chart showing an operation of the conventional test circuit 81. As shown in FIG. 9, an external write command signal and an external clock signal transmitted from a tester (not shown) are received in the flip-flop 82. In the flip-flop 82, an internal write command signal is set to a high level at a time T91 in synchronization with a leading edge of a pulse of the external clock signal in a time-period (from a time T90 to a time T92) in which the level of the external write command signal is set to a low level, and the level of the internal write command signal is changed to a low level at a time T93 in synchronization with a leading edge of a next pulse of the external clock signal in a time-period (after the time T92) in which the level of the external write command signal is set to a high level. Because the low level time-period of the external write command signal is equal to the pulse repetition period of the external clock signal, the internal write command signal is set to the high level during a time-period (from the time T91 to the T93) equal to the pulse repetition period of the external clock signal. The internal write command signal is transmitted from the flip-flop 82 to the memory cell array 84.
Also, the external clock signal and an external pre-charge command signal transmitted from the tester are received in the flip-flop 83. The external pre-charge command signal is set to a low level during a time-period (from the time T92 to a time T95) which is equal to the pulse repetition period of the external clock signal and is later than the low level time-period of the external write command signal by the pulse repetition period of the external clock signal. In the flip-flop 83, an internal pre-charge command signal is set to a high level at the time T93 in synchronization with a leading edge of a pulse of the external clock signal in the time-period (from the time T92 to a time T95) in which the level of the external pre-charge command signal is set to a low level, and the level of the internal pre-charge command signal is changed to a low level at the time T94 in synchronization with a leading edge of a next pulse of the external clock signal in a time-period (after the time T95) in which the level of the external pre-charge command signal is set to a high level. The internal pre-charge command signal is transmitted from the flip-flop 83 to the memory cell-array 84.
In the memory cell array 84, an operation test of memory cells is performed in a write recovery time-period (from the time T91 to the time T93) determined by a leading edge of the internal write command signal and a leading edge of the internal pre-charge command signal. Therefore, the write recovery time-period depends on the pulse repetition period of the external clock signal.
However, because the pulse repetition period of the external clock signal is longer than that of a clock signal which is actually used in a normal operation of a semiconductor memory represented by the SDRAM 80, an operational performance of the semiconductor memory cannot be reliably tested. Therefore the judgment whether or not an operational performance of the semiconductor memory satisfies specifications required of the semiconductor memory cannot be performed in a wafer test. Therefore the judgment is performed in a final test when the semiconductor memory is packaged, and a semiconductor memory not satisfying the specifications required of the semiconductor memory is abandoned. Therefore there is drawbacks that the test performed for the semiconductor memory is troublesome and the semiconductor memory cannot be manufactured at a low cost.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional test circuit, a test circuit of a semiconductor memory in which the judgment whether or not an operational performance of the semiconductor memory satisfies specifications required of the semiconductor memory is reliably performed in a wafer test even though an external clock signal having a pulse repetition period longer than that of a clock signal, which is used to operate the semiconductor memory while satisfying the specifications, is used in the wafer test.
The object is achieved by the provision of a test circuit of a semiconductor memory, comprising internal clock enabling signal producing means for producing an internal clock enabling signal set to a first level from a first write recovery test signal set to the first level and an external clock enabling signal, of which a phase is shifted from that of an external clock signal by xc2xdL (L is a positive integer higher than 1) of a pulse repetition period of the external clock signal or which is set to a second level; internal clock signal producing means for producing an internal clock signal, of which a pulse repetition period is, 1/N (N is a positive integer, and N=L for the positive integer higher than 1) of the pulse repetition period of the external clock signal, from the internal clock enabling signal produced by the internal clock enabling signal producing means, the external clock signal, the first write recovery test signal set to the first level and the external clock enabling signal; internal write command signal and internal pre-charge signal producing means for producing an internal write command signal and a first pre-charge signal, of which a leading edge is shifted from that of the internal write command signal by xc2xdN of the pulse repetition period of the external clock signal, from the internal clock signal produced by the internal clock signal producing means, an external write command signal set to the second level, the first write recovery test signal set to the first level and the external clock signal; and a first selector for outputting the first pre-charge signal produced by the internal write command signal and internal pre-charge signal producing means to a memory cell array as an internal pre-charge command signal to test an operational performance of the memory cell array according to a write recovery time-period which is determined from the internal pre-charge command signal and the internal write command signal produced by the internal write command signal and internal pre-charge signal producing means and is equal to xc2xdN of the pulse repetition period of the external clock signal.
In the above configuration, a write recovery time-period shorter than the pulse repetition period of the external clock signal is prepared from the first pre-charge signal and the internal write command signal produced in the test circuit comprising the internal clock enabling signal producing means, the internal clock signal producing means, the internal write command signal and internal pre-charge signal producing means and the first selector.
Accordingly, even though an external clock signal having a pulse repetition period longer than that of a specific clock signal, which is used to operate the semiconductor memory while satisfying specifications required of the semiconductor memory, is used in a wafer test because a cheap tester generates only the external clock signal having the pulse repetition period longer than that of the specific clock signal, an internal clock signal having a pulse repetition period equivalent to that of the specific clock signal can be easily produced. Therefore the judgment whether or not an operational performance of the semiconductor memory satisfies the specifications can be reliably performed in the wafer test, and a semiconductor memory not satisfying the specifications required of the semiconductor memory can be abandoned.
Also, because it can be judged in the wafer test whether or not the operational performance of the semiconductor memory satisfies the specifications, the specification test of the semiconductor memory in a final test can be omitted. Therefore, a test cost of the semiconductor memory can be reduced.
It is preferred that the internal clock signal producing means comprises a first AND gate for producing a first AND gate signal, of which the phase is the same as that of the external clock enabling signal, from the first write recovery test signal and the external clock enabling signal of which the phase is shifted from that of the external clock signal by xc2xc of the pulse repetition period of the external clock signal or which is set to the second level; an EXOR gate for producing an EXOR gate signal, of which a pulse repetition period is half of that of the external clock signal or of which the phase is the same as that of the external clock signal, from the first AND gate signal produced in the first AND gate and the external clock signal; and a second AND gate for producing the internal clock signal, of which a pulse repetition period is half of that of the external clock signal or of which the phase is the same as that of the external clock signal, from the EXOR gate signal produced in the EXOR gate and the internal clock enabling signal.
In the above configuration, the internal clock signal, of which a pulse repetition period is half (corresponding to N=2) of that of the external clock signal or of which the phase is the same (corresponding to N=1) as that of the external clock signal, can be reliably obtained.
It is also preferred that the internal clock enabling signal producing means comprises an NOR gate for producing an NOR gate signal, which is set to the second level, from the first write recovery test signal and a reset signal; and a first flip-flop for receiving the NOR gate signal produced in the NOR gate as a set signal and producing the internal clock enabling signal, which is set to the first level, from the set signal, the external clock enabling signal and the external clock signal.
In the above configuration, the internal clock enabling signal, which is set to the first level, can be reliably produced.
It is also preferred that the internal write command signal and internal pre-charge signal producing means comprises a second flip-flop for producing the internal write command signal from the external write command and the external clock signal; a third AND gate for producing a third AND gate signal from the internal write command signal produced in the second flip-flop and the first write recovery test signal set to the first level; and a third flip-flop for producing the first pre-charge signal from the third AND gate signal produced in the third AND gate and the internal clock signal.
In the above configuration, the internal write command signal and the first pre-charge signal can be reliably produced.
It is also preferred that the test circuit further comprises second control means for producing a second pre-charge signal, of which a leading edge is shifted from that of the internal write command signal by K/2N (K is a positive integer high than 1, and K less than 2N) of the pulse repetition period of the external clock signal, from the internal clock signal produced by the internal clock signal producing means and the first pre-charge signal produced by the internal write command signal and internal pre-charge signal producing means, wherein the first selector selects either the first pre-charge signal or the second pre-charge signal as the internal pre-charge command signal to test the operational performance of the memory cell array according to a write recovery time-period which is determined from the internal pre-charge command signal and the internal write command signal produced by the internal write command signal and internal pre-charge signal producing means and is equal to M/2N (M is a positive integer, and M less than 2N) of the pulse repetition period of the external clock signal.
In the above configuration, because the first pre-charge signal or the second pre-charge signal is output to the memory cell array as the internal pre-charge command signal, a write recovery time-period, which is equal to M/2N of the pulse repetition period of the external clock signal, can be determined, and the operational performance of the memory cell array can be tested according to the write recovery time-period.
It is also preferred that the second control means comprises a flip-flop for producing the second pre-charge signal, of which a leading edge is shifted from that of the internal write command signal by xc2xe of the pulse repetition period of the external clock signal, from the internal clock signal, of which a pulse repetition period is half of that of the external clock signal, and the first pre-charge signal of which a leading edge is shifted from that of the internal write command signal by xc2xc of the pulse repetition period of the external clock signal; and a second selector for selecting either the first pre-charge signal produced by the internal write command signal and internal pre-charge signal producing means or the second pre-charge signal produced in the flip-flop according to a second write recovery test signal, wherein the first selector selects the first pre-charge signal or the second pre-charge signal selected in the second selector as the internal pre-charge command signal according to the first write recovery test signal to test the operational performance of the memory cell array according to a write recovery time-period which is determined from the internal pre-charge command signal and the internal write command signal produced by the internal write command signal and internal pre-charge signal producing means and is equal to xc2xc or xc2xe of the pulse repetition period of the external clock signal.
In the above configuration, the second pre-charge signal is produced in the flip-flop, and the first pre-charge signal or the second pre-charge signal is selected in the second selector. In cases where the first pre-charge signal selected in the second selector is output to the memory cell array as the internal pre-charge command signal, the operational performance of the memory cell array can be tested in the write recovery time-period equal to xc2xc of the pulse repetition period of the external clock signal. Also, in cases where the second pre-charge signal selected in the second selector is output to the memory cell array as the internal pre-charge command signal, the operational performance of the memory cell array can be tested in the write recovery time-period equal to xc2xe of the pulse repetition period of the external clock signal.
It is also preferred that the internal clock signal, of which the phase is the same as that of the external clock signal, is produced by the internal clock signal producing means in cases where the external clock enabling signal set to the second level is input to the internal clock signal producing means, the level of the internal write command signal produced by the internal write command signal and internal pre-charge signal producing means is risen up in synchronization with a leading edge of the external clock signal, the level of the first pre-charge signal produced by the internal write command signal and internal pre-charge signal producing means is risen up in synchronization with a trailing edge of the internal clock signal to set a time difference in the leading edges between the first pre-charge signal and the internal write command signal to xc2xd of the pulse repetition period of the external clock signal, and the operational performance of the memory cell array is tested according to the write recovery time-period equal to xc2xd of the pulse repetition period of the external clock signal.
In cases where the external clock enabling signal is set to the second level, the internal clock signal, of which the phase is the same as that of the external clock signal, is produced. Therefore, the write recovery time-period is equal to xc2xd of the pulse repetition period of the external clock signal, and the operational performance of the memory cell array is tested in this write recovery time-period.